This research delves into the critical realm of space applications by conducting an experimental analysis and investigation into the effects of radiation on integrated circuits. As space missions become more advanced and extended, the resilience of electronic components, particularly integrated circuits, to radiation becomes paramount. Through rigorous experimentation, this study aims to enhance our understanding of the impact of radiation on integrated circuits and pave the way for the development of more robust and reliable technologies for space exploration.

Radiation resilience, integrated circuits, space applications

J. R. Schwank, “Basic Mechanisms of Radiation Effects in the Natural Space Environment,” Notes of the Short Course of the 1994 IEEE Nuclear and Space Radiation Effects Conference, Tucson (Arizona), July 1994, Section II, pp. 1-109.

J. C. Boudenot and E. Daly, “Radiation: Interaction Mechanisms and Environments, New Models of the Earth’s Radiation Environment”, Notes of the Short Course of the 2nd European Conference on Radiation and its Effects on Components and Systems, Saint-Malo (France), September 1993, Short Course 1, pp. 1-77.

D. R. Alexander, “Design issues for radiation tolerant microcircuits for space”, Notes of the Short Course of the IEEE Nuclear and Space Radiation Effects Conference, Indian Wells (California), July 1996, Section V.

H. Johnston, "The Influence of VLSI Technology Evolution on Radiation-Induced Latchup in Space Systems," IEEE Transactions on Nuclear Science, vol. 43, no. 2, April 1996, pp. 505-521.

G. Anelli, M. Campbell, M. Delmastro et al., “Radiation Tolerant VLSI Circuits in Standard Deep Submicron CMOS Technologies for the LHC Experiments: Practical Design Aspects”, presented at the IEEE Nuclear and Space Radiation Effects Conference (NSREC ’99, Norfolk, Virginia, USA, July 1999), IEEE Transactions on Nuclear Science, vol. 46, no. 6, December 1999, pp. 1690- 1696.

S. E. Kerns, B. D. Shafer, L. R. Rockett et al., “The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches,” Proceedings of the IEEE, vol. 76, no. 11, November 1988, pp. 1470-1509.

J. Yao, S. Okada, M. Masuda, K. Kobayashi, "DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test," IEEE Transactions on Nuclear Science, vol. 59, no. 6 , 2013.

J.M. Benedetto, D.B. Kerwin, J. Chaffee, "Radiation hardening of commercial CMOS processes through minimally invasive techniques," Proc. of the IEEE Radiation Effects Data Workshop, pp. 105-109, 1997.

Z. Jia, Y. Haigang, S. Jiabin, Y. Le, and W. Yuanfeng, "Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method," Journal of Semiconductors, Vol. 35, No. 8, 2014.

H. Johnston, "Radiation Effects in Advanced Microelectronics Technologies," IEEE Transactions on Nuclear Science, vol. 45, no. 3, June 1998, pp. 1339-1354.

F. Faccio, G. Anelli, M. Campbell et al., “Total dose and single event effects (SEE) in a 0.25 μm CMOS technology”, Proceedings of the Fourth Workshop on Electronics for LHC Experiments (LEB98, Rome, Italy, September 1998), pp. 105-113.

Dufour, P. Garnier, T. Carriere and J. Beaucour, “Heavy Ion induced Single Hard Error on sub micronic memories,” IEEE Transactions on Nuclear Science, vol. NS-39, no. 6, December 1992, pp. 1693-1697.