Purpose: This critical review systematically examines the complex interplay between ultra-low-power (ULP) design methodologies and the corresponding verification challenges in modern integrated circuits. The imperative for pervasive, battery-operated devices (IoT, wearables) has pushed design-for-power techniques to their limits, simultaneously creating significant hurdles for ensuring functional correctness. Methodology: The paper first establishes the theoretical foundation of power dissipation in CMOS circuits, followed by a systematic survey of leading ULP design techniques, including dynamic voltage/frequency scaling, power gating, and multi-threshold CMOS. It then evaluates state-of-the-art power estimation and, crucially, formal and simulation-based methodologies necessary for verifying the functional integrity and power intent, as formalized by the Unified Power Format (UPF). Findings: Aggressive power reduction techniques, particularly power gating, fundamentally alter the circuit's state and timing characteristics, rendering traditional verification flows insufficient. Formal verification, specifically equivalence checking and property checking based on Satisfiability (SAT) and Binary Decision Diagrams (BDD), is increasingly indispensable for exhaustively validating power management logic and state retention mechanisms.

Originality: This review offers a holistic synthesis, bridging the gap between ULP design methodology and its formal verification requirements, providing a foundational resource for researchers and practitioners navigating the dual constraints of energy efficiency and functional integrity in next-generation VLSI.

Ultra-Low-Power Design, Power Gating, VLSI, Formal Verification, Unified Power Format (UPF), Power Estimation, CMOS

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